ISSCC 2007 / SESSION 18 / SRAM / 18 . 4 18 . 4 A 65 nm 8 T Sub - Vt SRAM Employing Sense - Amplifier Redundancy
نویسندگان
چکیده
The subthreshold regime is a critical biasing space as it enables minimum energy operation for logic circuits [1]. However, practical systems rely heavily on SRAMs, which conventionally limit the minimum VDD to above Vt. SRAMs often dominate the total die area and power, and minimizing their energy requires scaling VDD as low as possible. In this work, a 256kb SRAM in 65nm CMOS is presented that operates in sub-Vt (at 350mV) despite the exponential effect Vt variations have on device strength.
منابع مشابه
Ultra Low-Power Fault-Tolerant SRAM Design in 90nm CMOS Technology
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